An analog/digital converter (hereinafter, referred to as ADC) is required for a computer that is operated by a digital signal to process physical information converted into an analog electrical signal by a sensor.
High performance is always required for the ADC used in a measuring device according to requirement of performance improvement of a measuring apparatus such as an inspection apparatus that is used for manufacturing semiconductors in which miniaturization is processed and a medical diagnostic apparatus having a high speed and high resolution for more accurate diagnosis.
However, a speed of single ADC that can perform sampling while maintaining an effective resolution in 10 bit or more may be limited to approximately 250 MHz from rate-limiting derived from frequency characteristics of a transistor configuring the ADC.
Thus, a technique called time interleaving has been noted in which a plurality of ADCs are parallelized, time difference is provided in each sampling timing, and high speed of a conversion speed is achieved as a whole.
For example, it is possible to perform the sampling at a speed of 1/1 [ns]=1 [GS/s] as a whole by connecting four unit ADCs of 8 [bit] and 250 [MS/s] ([S/s] is a unit representing the number of times of samplings in 1 [s]; when an interval of the sampling is T, T=1/250 [MS/9]=4 [ns]) to the same analog signal line in parallel and by performing the sampling by shifting the sampling timing by a width of 1 [ns]. Several ADCs having a sampling rate of a speed exceeding a performance limit of a CMOS transistor have been developed by using the technique.
Meanwhile, the technique is also limited in the resolution to be guaranteed due to mismatch such as DC offset of each ADC which is connected in parallel, variation of a conversion gain, and a deviation of sampling clock timing.
However, in recent years, also with respect to the problem, a scheme for correcting the mismatch between the ADCs in a digital signal region after AD converting is performed has been disclosed in PTLs 1 and 2, or NPLs 2 and 3, and the mismatch problem is headed to be solved.
However, the mismatch problem is solved and a clue is found in the improvement of the effective resolution while maintaining the high speed of the interleaved ADC, but new problem occurs.
Here, NPL 1 illustrates a typical configuration example of the interleaved ADC. In NPL 1, the ADCs are realized in which 80 ADCs of 250 MS/s and 8 bits are connected in parallel and which have the sampling rate of 20 GS/s.
The technique takes a form in which the analog input signal transported to the ADC is received at a high speed buffer and is distributed in an ADC sampling circuit (circuit described as 80 T/H in NPL 1) connected in parallel to a subsequent state.
However, each ADC sampling circuit releases an electric charge with respect to an input in a sampling clock edge and another parallel ADC samples the signal disturbed by the electric charge, and thereby a problem that the effective resolution is limited occurs. Here, it is important that the digital correction scheme cannot be effective against irregular factors and leads to a decrease in the effective resolution.
Since the electric charge released from the input of the ADC irregularly depends on the input signal, an existing digital correction scheme cannot be applied. In NPL 1, this issue is not a problem if a target of the effective resolution is 8 bit, but a new problem to be a barrier occurs in realizing the resolution greater than this.